Biasing

YOU WILL BE ABLE TO

Explain why an amplifier needs a bias point in saturation.
Design a gate divider with source degeneration.
Verify the operating region after biasing.
Explain how source degeneration stabilises the bias against device spread.

A MOSFET used as a switch lives at the two ends of its range. A MOSFET used as an AMPLIFIER must sit somewhere in the middle, in saturation, so that small changes in $V_{GS}$ produce proportional changes in $I_D$ — with room to swing in both directions without leaving the region. Establishing that resting point with DC components is biasing, and it is the necessary preparation for the small-signal amplifiers of ME-3.

Gate-divider bias with source degeneration: R_1 and R_2 set the gate voltage, R_S sets the current, R_D sets the output swing.

Read the circuit in the order it was designed. $R_1$ and $R_2$ form a CA-2 voltage divider setting the gate voltage $V_G$ — and because the gate draws no current, that divider is unloaded, so the plain divider formula applies exactly (contrast the loading trap of CA-2 L3, which does not apply here). $R_S$ carries the drain current to ground, lifting the source to $V_S = I_D R_S$ . Since $V_{GS} = V_G - V_S$ , the source resistor participates in setting the very current that flows through it. $R_D$ converts drain current into an output voltage swing.

V_G = V_{DD}\frac{R_2}{R_1 + R_2}

V_{GS} = V_G - I_D R_S

V_D = V_{DD} - I_D R_D

the three design equations

WORKED EXAMPLE

A bias design, start to finish

Target: $I_D = 2$ mA from $V_{DD} = 10$ V, using a device with $V_{th} = 1$ V and $k_n = 1$ mA/V $^2$ .
Required overdrive: $I_D = \tfrac{1}{2}k_n V_{OV}^2 \Rightarrow V_{OV} = \sqrt{2 I_D / k_n} = \sqrt{4} = 2$ V, so $V_{GS} = 3$ V.
Choose $V_S = 2$ V (a common rule of thumb: a fifth or so of the supply, enough for the feedback to bite). Then $R_S = V_S / I_D = 2\ \text{V}/2\ \text{mA} = 1$ kΩ.
Gate voltage: $V_G = V_{GS} + V_S = 3 + 2 = 5$ V. A divider of two equal resistors gives half the supply — use $1$ MΩ each, high values being harmless since the gate draws nothing.
Choose $V_D = 6$ V, leaving swing room both ways: $R_D = (10 - 6)/2\ \text{mA} = 2$ kΩ.
VERIFY the region: $V_{DS} = V_D - V_S = 6 - 2 = 4$ V, and $V_{OV} = 2$ V. Since $4 \ge 2$ , the device is in saturation with $2$ V of margin. The design holds.

R_1 = R_2 = 1

MΩ,

R_S = 1

kΩ,

R_D = 2

kΩ, biased at

2

WORKED EXAMPLE

The verification step is not optional

Suppose the same design had chosen $R_D = 4$ kΩ instead, chasing more gain.
Then $V_D = 10 - (2\ \text{mA})(4\ \text{k}\Omega) = 2$ V, and $V_{DS} = 2 - 2 = 0$ V.
$V_{DS} = 0 < V_{OV} = 2$ V: the device has fallen out of saturation into triode. The square-law current assumption that produced these numbers is no longer valid, so the whole calculation is self-contradictory.
Always finish a bias design by checking the region. A bias point that fails this check does not just perform poorly — it invalidates the arithmetic that produced it.

R_D = 4

kΩ is not a lower-performing design; it is an inconsistent one.

PRACTICE

A gate divider uses $R_1 = 2$ MΩ (top) and $R_2 = 1$ MΩ (bottom) from a $9$ V supply. Find $V_G$ , and explain why the divider formula applies exactly here.

A MOSFET with $V_{th} = 1.5$ V and $k_n = 2$ mA/V $^2$ is to be biased at $I_D = 4$ mA. Find the required $V_{GS}$ .

Continuing problem 2: with $V_G = 5$ V, find $R_S$ , and then find the largest $R_D$ that keeps the device in saturation from a $12$ V supply.

Two devices from the same bin have $V_{th}$ differing by $0.3$ V. Explain qualitatively what source degeneration does to the resulting difference in $I_D$ , compared with a circuit biased by the gate divider alone.