← PS-3 · THE BITSY BOARD CHALLENGE

Final validation

YOU WILL BE ABLE TO
  • Run a full-system audit against all ten rules from memory.
  • Read a 24-component schematic methodically, by subsystem.
  • State what the engine checks and what it honestly does not.
  • Take a design to fab-ready output, with the last verification step a viewer, not a click.

A finished design earns a FINAL PASS — not because the tools missed something, but because system-level reading catches what part-level reading cannot. The discipline: regenerate clean; audit the rules; walk the schematic by subsystem; route the layout; and inspect the fab files with your own eyes before anything is manufactured.

The rules audit is now something you can do from memory: ask the engine for its ten rules at /api/parts and each one's enforcedBy. Validated clauses (V2 through V8), construction guarantees, and — since the library grew — zero unenforced. Read the list against YOUR board: every LED's resistor placed, every required signal named, every pin unique and legal, the analog sensor on an analog pin. Ten rules, one pass, no exceptions to carry in your head.

Then the schematic, and 24 components is where method beats staring: audit by SUBSYSTEM, exactly the decomposition of Lesson 1 run in reverse. Six LED pairs; two buttons; buzzer and its resistor; the pixel trio; the divider pair; two headers; the MCU. Tick each ledger line as you find it, walk the ground net once, and the page is read — the same finger-on-net habit from PS-2, scaled up by discipline rather than effort.

Last, the output. Route the PCB — the Bitsy's reference layout runs 42 copper traces, and your PS-2 invariant predicts the count from the trace ledger. Export the Gerbers: eleven files — four front layers (copper, silkscreen, mask, paste), four back, the board outline, the fabrication layer, and the drill file. And then the step no button replaces: OPEN THE ZIP IN A GERBER VIEWER and look. Automated checks proved the design obeys its rules; only inspection proves the files say what you meant. Fab houses offer free viewers precisely because engineers who skip this step ship their mistakes at production speed.

WORKED EXAMPLE

The audit, timed

  1. A classmate's "finished" Bitsy clone reports 23 components. Diagnose by ledger before opening the spec.
  2. One component short means a one-component line is missing: a button or a header — an LED pair would be two short, the pixel trio three.
  3. The trace count tells them apart: a missing button takes 2 traces (42 left), the servo header 3 (41), the eyes header 4 (40). The engine reports 42 — a button.
  4. Subsystem counts localise it in two subtractions, which is the entire argument for auditing by subsystem instead of recounting the page.
A missing button — found from the ledger, confirmed by the trace count, before the spec was opened.

PRACTICE

Q1

Recite the three enforcement classes with one current example each.

Q2

Your board validates clean. Name two ways it can still be wrong, and whose gate catches each.

Q3

Why does the Gerber zip contain both a paste layer and a mask layer?

Q4

The reference layout routes 42 traces from a 44-trace schematic. Reproduce the PS-2 invariant's arithmetic for this board.

Final validation · PS-3 · iLearnSTEM Electronics