Logic gates from MOSFETs

YOU WILL BE ABLE TO

Explain how voltage levels represent logical values.
Describe the CMOS inverter's operation from ME-2's switch model.
Explain why CMOS dissipates power almost only while switching.
Describe how NAND and NOR are built from complementary pairs.

Everything so far has treated voltage as a continuous quantity to be measured. Digital logic makes a deliberate sacrifice: it agrees to notice only two ranges of voltage, calls them $0$ and $1$ , and throws away everything in between. In exchange it gets something analogue circuits can never have — signals that regenerate perfectly at every stage, so noise and distortion do not accumulate across a million gates. On a $3.3$ V board, anything below roughly $0.8$ V is a logical $0$ , anything above roughly $2.0$ V is a $1$ , and the gap between is a forbidden zone that well-designed circuits cross as fast as possible.

The device that does the work is the MOSFET of ME-2, used exactly as that unit's Lesson 3 described: driven hard between cutoff and deep triode, an open switch or a small resistance, never lingering in between. What is new here is using two complementary devices together — an n-channel and a p-channel — which is what the C in CMOS stands for.

The CMOS inverter: two switches in series between the rails, driven by the same input. Exactly one is ever on.

Read it with ME-2's rules. Drive the input HIGH: the n-channel device sees $V_{GS} = V_{DD}$ , well above threshold, and turns on, pulling the output down to ground. The p-channel device sees $V_{GS} = 0$ relative to its source at $V_{DD}$ , so it is off. Drive the input LOW and both reverse: the p-channel turns on and pulls the output up to $V_{DD}$ , the n-channel is off. Either way the output is the opposite of the input, and — the crucial part — it is connected to a rail through a switch that is fully on, so it reaches the rail exactly, not approximately.

$v_{in}$	$M_p$	$M_n$	$v_{out}$
0	on	off	1
1	off	on	0

The CMOS inverter, both states. Note that no state has both devices conducting.

Larger gates follow the same complementary recipe. A two-input NAND puts two n-channel devices in SERIES between the output and ground — so the output is pulled low only when both inputs are high — and two p-channel devices in PARALLEL to $V_{DD}$ , so either input being low pulls the output high. NOR is the exact dual: n-channel devices in parallel, p-channel in series. Every gate is built this way, which means NAND and NOR are the cheapest gates in silicon — four transistors each — while AND and OR cost six, because they are a NAND or NOR followed by an inverter.

WORKED EXAMPLE

Counting transistors

Inverter: 2 transistors. NAND2: 4. NOR2: 4.
AND2 = NAND2 + inverter = 6. OR2 = NOR2 + inverter = 6.
So a designer working in silicon prefers NAND and NOR, and rewrites logic to use them — which is why Lesson 2's universality result matters commercially, not just theoretically.
A gate's cost is transistor count and its speed is roughly the number of devices in series in the pull-up or pull-down path, which is why 8-input gates are usually built as trees of 2-input gates rather than eight series devices.

NAND and NOR are cheapest; AND and OR are those plus an inverter.

WORKED EXAMPLE

Switching energy, quantified

A gate drives a load capacitance of $20$ fF and switches at $100$ MHz on a $1.2$ V supply.
Energy per transition: $\tfrac{1}{2}Cv^2 = 0.5 \times 20\times10^{-15} \times 1.44 \approx 1.44\times10^{-14}$ J.
Power at $10^8$ transitions per second: $\approx 1.4$ µW per gate.
One gate is nothing; a billion of them is over a kilowatt, which is precisely why chip designers care about every femtofarad and every unnecessary transition.

≈ 1.4 µW per gate — trivial alone, decisive in aggregate.

PRACTICE

On a $3.3$ V board, a signal measures $1.4$ V. Is it a logical 0, a logical 1, or neither?

In a CMOS inverter with the input at $0$ V, which device conducts and what is the output?

Why does a CMOS gate draw almost no current when its inputs are steady, and what does it draw current for?

A design needs an AND gate. Explain why building it as a NAND followed by an inverter is the normal approach in silicon rather than a wasteful detour.