Digital logic

The logic inside the pin

Every GPIO you have used in this course is a digital port built from this unit's circuits: an output driver that is a CMOS inverter scaled up, an input with defined thresholds, and — on the input path — flip-flops that sample the pin in step with the microcontroller's clock. This capstone traces that path and computes the timing that governs it.

1. The RP2040's GPIO output driver is a CMOS pair like Lesson 1's inverter, sized to source or sink about $12$ mA. Using ME-2's conduction-loss expression and a plausible on-resistance of $50\ \Omega$, compute the voltage drop and power dissipation when the pin drives $12$ mA, and comment on whether the pin can be treated as an ideal $3.3$ V source.
2. The pin's input path samples through flip-flops clocked at the system clock, nominally $125$ MHz. Compute the clock period, and state the longest a signal could sit unnoticed before the next sampling edge.
3. Your ME-2 capstone drove a WS2812 strip whose bit period is about $1.25$ µs. How many $125$ MHz clock cycles is that, and why does that ratio make bit-banging the protocol in software feasible but fragile?
4. A pushbutton on a GPIO needs two separate treatments from this unit and from CA-5. Name both, state which problem each solves, and size the RC debounce using your CA-5 capstone's method for a $10$ ms time constant.
5. Compute a timing budget: if reading the pin, deciding, and driving another pin takes $t_{cq} = 3$ ns, $t_{logic} = 5$ ns, $t_{setup} = 1$ ns, what is the fastest clock that path supports, and is $125$ MHz within it?
6. In PCB Studio, build a board with the Pico 2 W, a pushbutton, and the ws2812_strip8, and generate the schematic. Identify the button's input pin and the strip's data pin. Every edge on that data line is this unit's subject matter: a CMOS driver switching, a transmission line settling, and a receiver sampling with setup and hold requirements of its own.