Flip-flops & registers

YOU WILL BE ABLE TO

Explain how cross-coupled gates store a bit.
Describe the SR latch and its forbidden input.
Distinguish level-triggered latches from edge-triggered flip-flops.
Describe a register as a group of flip-flops.

Combinational logic has no memory: remove the inputs and the outputs forget. Feed an output back to an input, however, and the circuit can hold a state — the same feedback idea that stabilised bias points in ME-2 and set gains in ME-4, now applied to keep a value rather than to control one. Two cross-coupled NAND gates are the simplest memory in existence.

The NAND-based SR latch: each gate's output feeds the other's input, so the pair has two stable states.

The inputs are active-low, written $\overline{S}$ and $\overline{R}$ — pulling one low commands an action. Hold both high and the latch simply remembers: whichever output was high stays high, because each gate's output is sustaining the other's input. Pull $\overline{S}$ low and $Q$ is forced high — set. Pull $\overline{R}$ low and $Q$ is forced low — reset. Pull both low and both outputs go high, which contradicts the whole premise that they are complements, and when you release them the final state depends on which input rises last: a race. That combination is forbidden.

$\overline{S}$	$\overline{R}$	$Q$	$\overline{Q}$	meaning
1	1	hold	hold	remember
0	1	1	0	set
1	0	0	1	reset
0	0	1	1	forbidden

The NAND SR latch. The both-low row is forbidden because the outputs stop being complementary.

The D flip-flop is the workhorse: one data input, one clock, one output, and a single rule — on each active clock edge, $Q$ takes the value $D$ had at that instant. Everything else it does follows from that. Group $n$ of them sharing one clock and you have an $n$ -bit register, which is what holds a variable in a processor; chain them so each one's output feeds the next one's input and you have a shift register, which is how serial data becomes parallel and how the WS2812 strip from ME-2's capstone accepts its colour bytes.

CLK	$D$	$Q_{next}$
rising edge	0	0
rising edge	1	1
0 or 1 (steady)	X	$Q$ (unchanged)
falling edge	X	$Q$ (unchanged)

The D flip-flop: the output changes only on the rising clock edge.

WORKED EXAMPLE

Walking the latch through a sequence

Start with $\overline{S} = \overline{R} = 1$ and $Q = 0$ .
Pull $\overline{S}$ low: $Q$ goes high. Release it back to 1: $Q$ stays high — the latch remembers.
Pull $\overline{S}$ low again: nothing changes, because $Q$ is already set. Setting an already-set latch is harmless.
Pull $\overline{R}$ low: $Q$ returns to 0, and stays there when released.

Two inputs, four operations, one stored bit.

WORKED EXAMPLE

A shift register moves data

Four D flip-flops in a chain share a clock; the first one's $D$ is the serial input.
Present the bit sequence $1, 0, 1, 1$ , one bit per clock edge.
After four edges the four flip-flops hold $1, 1, 0, 1$ — the sequence, in parallel, in reverse arrival order.
This is exactly how a microcontroller's SPI peripheral transmits and receives, and why one clock plus one data wire can carry arbitrarily many bits.

Serial in, parallel out, one bit per clock edge.

PRACTICE

A NAND SR latch has $\overline{S} = 1$ and $\overline{R} = 1$ . What does $Q$ do?

Why is $\overline{S} = \overline{R} = 0$ forbidden?

State the difference between a D latch and a D flip-flop in one sentence each.

An 8-bit register is built from D flip-flops sharing one clock. How many flip-flops, and what happens to all eight bits on a clock edge?