Timing and clocks

YOU WILL BE ABLE TO

Read a timing diagram.
Define setup and hold times and explain why they exist.
Compute the maximum clock frequency from propagation delays.
Explain metastability and why asynchronous inputs need synchronising.

A synchronous circuit's correctness is not just a matter of logic being right — it is a matter of signals arriving on time. The clock defines "on time": a periodic square wave whose edges are the instants at which every flip-flop in the design samples its input. A timing diagram plots the relevant signals against a common time axis, and reading one fluently is a basic skill.

A timing diagram: D changes between edges, and Q takes D's value at the following rising clock edge.

A flip-flop cannot sample instantaneously. Its input must be stable for a short interval BEFORE the clock edge — the setup time — and must remain stable for a short interval AFTER it — the hold time. These are not arbitrary specifications: internally the flip-flop is a small feedback circuit that needs time to commit to a state, exactly the settling behaviour CA-5 described. Violate setup or hold and the flip-flop may capture the wrong value, or worse.

Setup time, combined with the delay through the logic between flip-flops, sets the maximum clock speed. In one clock period, a signal must leave one flip-flop, propagate through the combinational logic, and arrive at the next flip-flop with setup time to spare:

T_{clk} \ge t_{cq} + t_{logic} + t_{setup}

the timing constraint — clock-to-output, logic delay, setup

The longest such path in a design is the critical path, and it alone determines the maximum frequency — a chip's clock speed is set by its single slowest route. Making a design faster therefore means finding that path and shortening it, usually by splitting the logic across two clock cycles (pipelining), which is why processors have deep pipelines.

WORKED EXAMPLE

Maximum clock frequency

A design has $t_{cq} = 2$ ns, worst-case combinational delay $t_{logic} = 6$ ns, and $t_{setup} = 1$ ns.
Minimum period: $T \ge 2 + 6 + 1 = 9$ ns.
Maximum frequency: $f = 1/9\ \text{ns} \approx 111$ MHz.
Halve the logic delay by pipelining and the period drops to $6$ ns — about $167$ MHz — from the same gates, rearranged.

≈ 111 MHz, rising to ≈ 167 MHz if the critical path is halved.

WORKED EXAMPLE

Why a button needs a synchroniser AND a debouncer

A pushbutton is asynchronous to the clock, so its edge can land inside a setup window: metastability. The fix is two cascaded flip-flops.
It is also mechanically noisy, chattering for milliseconds: the fix is CA-5's RC time constant, or a counter in logic that requires the level to be stable for many clocks.
These are different problems with different cures, and each is needed. A debounced signal can still be metastable; a synchronised signal can still bounce.
ME-6 builds the practical version of both.

Synchronise for the clock domain, debounce for the mechanics — both, always.

PRACTICE

A flip-flop specifies $t_{setup} = 0.8$ ns. What does that require of its data input?

A path has $t_{cq} = 1.5$ ns, $t_{logic} = 4$ ns, $t_{setup} = 0.5$ ns. Find the minimum clock period and the maximum frequency.

In the design above, what is the effect of adding a gate with $0.7$ ns of delay to the critical path?

Explain why an external sensor pulse must pass through two flip-flops before the rest of a synchronous design uses it.